One method for determining the current through a load in a circuit is to use a metal oxide semiconductor field effect transistor (MOSFET) for current sensing. Current sensing power MOSFETs conventionally include several thousand transistor cells arranged in parallel and sharing common drain, source and gate electrodes. Each transistor cell or element within the device is identical and current applied at the drain terminal of the device is shared equally between them. In such designs, it is common that the source electrodes of several of the transistors are separated from the remaining source electrodes and connected to a separate source terminal. Accordingly, the resulting current sensing MOSFETs can be thought of as equivalent to two or more transistors in parallel having common gate and drain terminals, but separate source terminals. The first of these transistors, including the majority of the transistor cells in the current sensing power MOSFET, is commonly referred to as the main FET. The second, including the several transistor cells having a separate source terminal, is referred to as the sense FET.
In use, the sense FET conducts only a small fraction of current applied to the common drain terminal, the fraction being inversely proportional to a sense ratio, n, which is a current ratio dependent on the ratio of the number of transistor cells in the main FET to those in the sense FET. The sense ratio n is defined for a condition in which the source terminals of the sense and main FETs are held at the same potential. When the sense ratio is known, the total current flowing through the device, and therefore the load current of a load to which the device is connected, can be calculated from a measurement of the source current of the sense FET, i.e. the current flowing in the current path of the sense FET, between the drain and source electrodes.
U.S. Pat. No. 5,079,456 discloses method and apparatus for measuring and/or controlling the level of current in a Sense FET which includes a power transistor and a sense transistor. Both transistors are biased to operate in a linear mode, and the source-drain voltage Vds of the sense transistor is compared to a predetermined fraction of the Vds of the power transistor. A control signal is generated that is representative of the results of the comparison, and, in one embodiment, that control signal is used in a feedback arrangement to drive the Vds of the sense transistor to the predetermined fraction of the Vds of the power transistor. Consequently, the level of current carried by the sense transistor is caused to be equal to the same predetermined fraction of the current carried by the power transistor.
U.S. Pat. No. 5,408,141 discloses an integrated power device comprising a power transistor and five of sense transistors. Four of the sense transistors are proportionate in size to the power transistor and are constructed around the periphery of the active area occupied by power transistor using the same process that are used to construct the components of the power transistor. The fifth sense transistor is located within the interior of the active area occupied by power transistor and contact is made to the necessary source region of the fifth senses transistor using a second level of metal interconnect to form a source contact.
U.S. Pat. No. 5,962,912 discloses a power semiconductor component having a cell structure includes a metallic resistance track that is insulated from the semiconductor body of the power semiconductor component and from a control electrode by a non-conductive layer. The resistance track is provided in a lateral region between cells of the power semiconductor. The active area of the component is not made smaller by the presence of the resistance track and the resistance track is produced simultaneously with a metallic layer of the component which provides electrical contact with a main electrode of the power semiconductor so that no additional manufacturing steps are required for adding the resistive track.
However, the wire bonding between the sense FET and the main FET will affect the performance of the device. Furthermore, it would be desirable to develop a power device integrating one or multiple sense FETs into one discrete power MOSFET, in a manner which does not increase number of mask layers and manufacturing process sequences. It is within this context that embodiments of the present invention arise.